1. Field of the Invention
The present invention relates to electronic design automation (EDA) systems. More particularly, the present invention relates to memory modeling for use with EDA tools.
2. Description of the Related Art
The design process for integrated circuits typically involves multiple transformations of a design from an initial idea to a functional, manufacturable product. A chip architect or designer begins with a design idea and then generates a corresponding behavioral definition of the design. The behavioral design results in a flow chart or a flow graph using which the designer can design the system data path and the registers and logic units necessary for implementation of the design. After the designer designs buses for coordinating and controlling the movement of data between registers and logic units, the data registers, buses, logic units, and their controlling hardware are implemented using logic gates and flip-flops. The result of this design stage is a netlist of gates and flip-flops. The netlist can be used to create a simulation model of the design to verify the design before provide the information needed by a routing software package to complete the actual design. The netlist of gates and flip-flops is thus transformed into a transistor list or layout and gates and flip-flops are replaced with their transistor equivalents or library cells. Timing and loading issues are also addressed during this cell and transistor selection process. Finally, the manufacturing process begins when the transistor list is implemented in a programmable logic device such as an FPGA or when the layout specification is used to generate masks for integrated circuit fabrication.
EDA tools improve upon this design process by permitting electronic circuit designers to more quickly and inexpensively design and verify their designs. FIG. 1 illustrates a typical design approach using EDA tools. The designer initially supplies a logic synthesis tool 120 with a high level language description 110 of the design and the logic synthesis tool 120 reduces the high level language description 110 to a low level or gate level description 130 of the design. Finally, verification or simulation of the design is performed by an engine 140 using a set of properties 150 or behaviors as an input to determine whether, and to what extent, the design described by HDL description 110 satisfies the properties 150. The properties 150 are based on a functional specification for the design being verified or simulated. A more detailed discussion of design verification and the use of properties can be found in U.S. patent application Ser. No. 09/447,085, filed Nov. 22, 1999, entitled “Static Coverage Analysis,” incorporated herein by reference.
The description of the design idea is typically written in a high-level hardware description language (“HDLs”) such as VHDL or Verilog. HDLs provide formats for representing the output of the various design stages described above and are thus used to create circuits at various levels of abstraction including gate-level descriptions of functional blocks and high-level descriptions of complete systems. HDLs provide a convenient format for the representation of functional and wiring details of designs and may represent various hardware components at one or more levels of abstraction. HDLs can be used to model many different kinds of hardware components or electronic circuits. VHDL and Verilog are commonly used to model circuits ranging from ALUs, arithmetic blocks, bus arbiters, bus interfaces, cache controllers, data paths, dual-phase clocks, instruction and address decoders, pipelines, reset circuits, sequencers, and state machines.
The design approach of FIG. 1 has also been previously used to model, synthesize, and verify memory circuit designs. However, prior art memory models suffered from two major disadvantages. First, they modeled every location of the memory even if only a subset of locations of the memory were actually used by the design. For example, if the designer is modeling a RAM having, for example, 1024 locations, the designer must provide a functional description for each location of the memory even if the design only accessed a small portion of the memory locations. The resulting memory model was inefficient and wasted valuable design resources. Second, memory models from one EDA tools vendor can typically only be used with simulation or verification engines from the same vendor. In other words, the choice to use a particular prior art memory model necessitated a particular verification or simulation engine. This lack of interoperability greatly limits the utility of prior art memory models.
Accordingly, there is a need for a means for modeling physical memory that more efficiently describes only those portions of a physical memory that are used by a given design. There is a further need for a memory model that is independent of the underlying simulation or verification engine and is thus interoperable with various simulation or verification engines.